A VRAM (video random access memory), sometimes called a dual port RAM (random access memory) or multiport DRAM (dynamic random access memory), is a DRAM having a serial access memory (SAM). The SAM permits a block of stored data to be rapidly accessed, while the normal access function of the DRAM is also occurring. The information in the SAM is normally obtained from, or input into, the DRAM portion of the VRAM which is accessed according to DRAM protocols.
Information may be written into the VRAM at DRAM address speeds and output through the serial access port, or vice versa. This is convenient for video applications because some address sequences, such as pixels in a raster scan, are predetermined.
In the mimed art multiport (DRAM), depicted in FIG. 1, an internally timed circuit triggers the latching of a helper flip-flop during a read operation of the serial access memory. Typically this internal timing is provided by a model built into the part. In FIG. 1 prior to the serial clock (SC), not shown, going high circuit 5 is turned on by ISOI, and a precharge circuit 10 is turned on by actuating transistors 15, 16, and 17 with the SPRE* signal. When SC goes high, circuit 10 is floated off and circuit 5 is off thereby isolating circuit 10 from circuit 20 which is strobed on. A decoder (not shown) is enabled before circuit 20 is strobed. The serial address is loaded to a counter (not shown) after the decoder is disabled. After the serial data is latched at NAND latch 30, all of the circuits 5, 10, 20, and 30 are returned to their respective normal states.
Loren L. McLaury's U.S. Pat. No. 5,325,502, entitled Pipelined SAM register Serial Output, is herein incorporated by reference to provide further background information.